Method and System for Emulating Content-Addressable Memory Primitives

ABSTRACT

A method and system for emulating content-addressable memory (CAM) primitives (e.g., a read operation) is disclosed. According to one embodiment, a method is provided for emulating a read operation on a plurality of CAM elements utilizing a read input including match input data and a CAM element selection index. In the described method, match reference data is distributed among a plurality of random-access memory (RAM) elements by storing match reference data corresponding to each of the plurality of CAM elements within a first RAM element of the plurality. Thereafter, a first record is identified within the first RAM element utilizing a first portion of the match input data and the CAM element selection index. A read operation result is then generated utilizing the first record.

PRIORITY CLAIM

The present application is a continuation of U.S. patent applicationSer. No. 11/083,209 (Atty. Docket No. ROC920050001US1), filed on Mar.17, 2005, and entitled, “Method and System for EmulatingContent-Addressable Memory Primitives,” which is incorporated herein byreference.

BACKGROUND

1. Technical Field

Embodiments of the present invention relate generally to data processingsystem memory resources and more particularly to a method and system foremulating content-addressable memory primitives.

2. Description of the Related Art

In a conventional data processing system, data and instructions arestored within memory storage elements arranged in a hierarchicalstructure. In a typical hierarchical memory or storage structure,smaller, faster memory elements are located closer (in terms of physicalstructure) and more tightly coupled (communicatively) to processingelements (e.g., processors or processor cores) and store a subset ofdata and/or instructions stored in larger, slower memory elements (e.g.,fixed or removable magnetic or optical disks, tape storage, or the like)elsewhere within or coupled to the data processing system. One type ofmemory element used frequently in data processing systems for so-called“main” or system memory is random-access memory.

In a conventional random-access memory or “RAM” element, data values arestored in an array of addressed memory locations. To perform a readoperation on a RAM element, an address (e.g., a data processing systemmemory address) is applied to the RAM element, causing data stored atthe applied address to be accessed and presented by the RAM.

In order to determine whether a particular data value is stored within aRAM element, an address-based data searching method is performed inwhich data values are sequentially read out from the RAM and comparedwith the searched-for data value. Specifically, a series of addressesare sequentially transmitted to an address port of the RAM, therebycausing data values to be read out from the memory locations addressed.A separate comparator element is then used to compare each of the outputdata values with the searched-for data value, generating a signal when amatch occurs. When a large number of data values is to be searched orcompared, such address-based search operations are very time consumingas only a single data value is typically processed each clock cycle.

Another type of memory element used in data processing systems toperform data search or comparison operations is content-addressablememory. In a content-addressable memory (CAM) element, a data value maybe searched by content, rather than address. In a conventional CAM, datavalues are stored such that each data value is assigned to a row orcolumn of an array of storage cells. To determine whether a particulardata value is stored in a CAM element, a content-based data matchoperation is performed in which a searched-for data value issimultaneously compared with all rows/columns containing the pre-loadeddata values. When one or more of the pre-loaded data values matches thesearched-for data value, a “match” signal is generated by the CAMelement, along with an address indicating the storage location (i.e.,row or column) of the matching pre-loaded data value.

By simultaneously comparing searched-for data with several pre-loadeddata values, a CAM element is able to perform comparison or matchingoperations involving several pre-loaded data values in a single clockcycle. Consequently, CAM elements significantly reduce the time neededto identify a specific data value within a large amount of data ascompared with conventional RAM elements and are used frequently forsearch or pattern-matching-intensive applications. FIG. 1 illustrates adata processing system processor cache as one such exemplaryapplication. The depicted data processing system processor cache 100includes a cache memory element 102 coupled to a cache tag lookupelement 104 as shown. For purposes of illustration, data processingsystem processor cache 100 will be described herein as a 32 kilobytecache having 1024 lines of 32 bytes each and organized as a 64-way setassociative cache including 16 sets.

Data processing system processor cache 100, as depicted in FIG. 1, isaddressed using a 32 bit address with bits 0 through 4 (represented asbits 4:0) identifying a specific byte within a cache line, bits 5through 8 (represented as bits 8:5) identifying a specific set of the 16possible sets, and remaining bits (represented as bits 31:9) making up a“cache tag” which identifies a block-frame address in memory where thecache line resides. In a conventional cache memory, a cache tag is usedto verify that the cache line addressed in fact stores the requesteddata.

Cache tag lookup element 104 includes a number of CAM elements 106A,106B, . . . 106N coupled to a multiplexer 108 and to a match indicationsignal generation element, (e.g., OR gate 110). In the illustrated dataprocessing system processor cache 100, 16 CAM elements 106 (one for eachcache “set”) are employed. In operation, a cache tag (e.g., bits 31:9 ofa data processing system memory address) is applied simultaneously toeach of CAM elements 106A-106N. Each of CAM elements 106A-106N in theillustrated processor cache is a 64×23 CAM including 64 23-bit registers(not illustrated) coupled to 64 comparators which are in turn coupled toencoding logic (not illustrated). Within the present description, thevariable “N” is intended to indicate some positive integer value andneed not indicate the same value consistently.

The encoding logic (not illustrated) of each of CAM elements 106 is usedto generate a 6-bit address corresponding to a matching CAM elementrecord. Each CAM element 106 is additionally coupled to OR gate 110 togenerate a match indication signal indicating whether or not a matchingrecord was identified. Each 6-bit CAM element address generated is thenapplied, along with a cache set index (e.g., bits 8:5 of the receiveddata processing system memory address), to multiplexer 108. Multiplexer108 outputs a selected input 6-bit address specified by the receivedcache set index. The output of multiplexer 108 is thencombined/concatenated with the cache set index to form a 10-bit cachememory element address as shown. The generated 10-bit cache memoryelement address is then used to address or identify a 256-bit line or“block” within cache memory element 102.

While CAM elements are well-suited for performing comparison operationssuch as those required by cache tag lookup element 104, CAMs may not beimplemented in some cases or may be prohibitively expensive in somecases where they may otherwise be used. One technique for providingbasic CAM functionality or “primitives” is to emulate the operation of aCAM element using one or more RAM elements. FIG. 2 illustrates aconventional RAM-based emulated CAM. The “virtual” or emulated CAMelement 200 depicted in FIG. 2 may be substituted for one of theindividual CAM elements 106A-106N illustrated in FIG. 1 and itsfunctionality, as applied for performing a portion of a cache tag lookupoperation, will be described with respect to data processing systemprocessor cache 100 of that figure. As represented in FIG. 2, emulatedCAM 200 includes RAM elements 202A, 202B, and 202C coupled withcombinatorial (e.g., AND gate 204 and OR gate 206) and encoding (e.g.,encoder 208) logic as shown.

Each RAM element 202 may be viewed as a 2-dimensional array of bitsincluding rows corresponding to each of the 64 ways of a cache memoryelement being accessed. Each row stores match reference data for aportion of a cache tag associated with the row's way and represented asa vector of bits. Accordingly, a 7-bit cache tag portion is representedusing a 2⁷-bit vector “one-hot” encoded to indicate, using a single bitvalue, which of the 128 possible cache tag portion permutations isstored within that row/way. Similarly, an 8-bit cache tag portion isrepresented using a 2⁸ or 256-bit vector.

In operation, emulated CAM 200, and associated RAM elements 202, areutilized to perform a “split” lookup function in which separate portions(e.g., a 7-bit portion and 2 8-bit portions) of a cache tag are eachused to address a corresponding one of RAM elements 202. A match of acomplete cache tag is indicated if each portion of the cache tag matchesin the same way of each of RAM elements 202 and consequently of thecache. For purposes of clarity, illustration of a write port (and acorresponding description of a write operation) has been omitted fromemulated CAM 200 of FIG. 2. Each cache tag portion identifies oraddresses a single bit position which may be viewed a column within anaccessed RAM element including a bit from each way. All 64 bits of thatbit position or column are then output to determine whether the providedor input partial cache tag value matched reference partial cache tagdata within the corresponding portion of the emulated CAM (indicated,for example, by a single bit having a logical “1” value).

The 64-bit outputs of each of RAM elements 202A-202C are then logicallycombined or “joined” via a bitwise AND operation using AND gate 204. Thecombined 64-bit output is then used to generate a 6-bit match addresscorresponding to a matching location within emulated CAM element 200(e.g., using encoder 208) and to generate a match indication signalindicating whether or not a matching record was identified (e.g., usingOR gate 206) as shown. If none of the bits of the bitwise-coalesced RAMelement output is set to a logical “1” value, a determination may bemade that the complete 23-bit input cache tag failed to match anemulated CAM element entry for a single way of an associated cachememory element. Once the 6-bit match address and match indication signalhave been generated, they may be applied, along with a CAM selection(e.g., cache set) index, to a multiplexer (e.g., multiplexer 108 ofFIG. 1) and used to address a cache memory element as previouslydescribed herein.

While RAM element-based CAM emulation may be utilized in somecircumstances where traditional CAMs may not, providing greaterflexibility and cost-effectiveness, one significant problem associatedwith such CAM emulation techniques is the quantity of RAM memoryrequired for implementation. This problem, although more prominent whereemulation of a CAM element is embodied in a single RAM, is evident evenwhere emulation is distributed across multiple RAM elements as depictedin FIG. 2. For example, for a 32 kilobyte cache as described herein, atleast 640 kilobits of RAM storage (approximately 40 kilobits of RAMstorage for each of a total of 16 emulated CAM elements) is required.

Additional RAM storage may also be required as a buffer for matchreference data used to update or modify match reference data within theemulated CAM's RAM elements. Moreover, logic used in conventionalCAM-based implementations (e.g., a multiplexer and an additional OR gateused to generate a global match indication signal) is not eliminated insuch CAM-emulation systems. In some circumstances this quantity ofmemory and logic is unacceptable and consequently a cache may be omittedor implemented in a less-than-optimal way.

SUMMARY

A method and system are provided for emulating content-addressablememory (CAM) primitives (e.g., a read operation). According to oneembodiment, a method is provided for emulating a read operation on aplurality of CAM elements using a read input including match input dataand a CAM element selection index. In the described method, matchreference data is distributed among a plurality of random-access memory(RAM) elements by storing match reference data corresponding to each ofthe plurality of CAM elements within a first RAM element of theplurality. Thereafter, a first record is identified within the first RAMelement using a first portion of the match input data and the CAMelement selection index. A read operation result is then generated usingthe first record.

The foregoing is a summary and thus contains, by necessity,simplifications, generalizations and omissions of detail; consequently,those skilled in the art will appreciate that the summary isillustrative only and is not intended to be in any way limiting. As willalso be apparent to one of skill in the art, the operations disclosedherein may be implemented in a number of ways including implementationin hardware using a variety of techniques. For example, implementationsof the present invention may be provided using application-specificintegrated circuits (ASICs) or other special-purpose electronic circuitsas well as programmable logic devices (PLDs) such as field-programmablegate arrays (FPGAs), programmable logic arrays (PLAs) or the like. Suchchanges and modifications may be made without departing from thisinvention and its broader aspects. Other aspects, inventive features,and advantages of the present invention, as defined solely by theclaims, will become apparent in the non-limiting detailed descriptionset forth below.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention may be better understood, and its numerousfeatures and advantages made apparent to those skilled in the art byreferencing the accompanying drawings in which:

FIG. 1 illustrates a data processing system processor cache including aconventional content-addressable memory-based cache tag lookup element;

FIG. 2 illustrates a conventional RAM-based emulated CAM element;

FIG. 3 illustrates a RAM-based emulated CAM element according to anembodiment of the present invention; and

FIG. 4 illustrates a flow diagram of a process for emulating a readoperation on a plurality of content-addressable memory elementsaccording to an embodiment of the present invention.

The use of the same reference symbols in different drawings is intendedto indicate similar or identical items.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

The following description and its accompanying figures sets forthembodiments for carrying out one or more method, systems, and/or devicesof the present invention. This description is intended to beillustrative rather than restrictive and should not be taken to belimiting. More specifically, in the following detailed description,numerous specific details such as specific method orders, structures,elements, and connections have been set forth. It is to be understoodhowever that these and other specific details need not be utilized topractice embodiments of the present invention. In other circumstances,well-known structures, elements, or connections nave been omitted, ornave not been described in particular detail in order to avoidunnecessarily obscuring the described invention embodiments.

References within the present description to “embodiments”, “oneembodiment” or “an embodiment” are intended to indicate that aparticular feature, structure, or characteristic described in connectionwith the embodiment is included in at least one embodiment of thepresent invention. The appearance of the phrase “in one embodiment” invarious places within the specification are not necessarily allreferring to the same embodiment, nor are separate or alternativeembodiments mutually exclusive. Moreover, various features are describedwhich may be exhibited by some embodiments and not by others. Similarly,various requirements may be described which are requirements for someembodiments but not other embodiments.

Embodiments of the present invention provide a method and system foremulating content-addressable memory (CAM) primitives (e.g., a readoperation) within a data processing system. According to one embodiment,a method is provided for emulating a read operation on a plurality ofcontent-addressable memory elements utilizing a read input (e.g., a dataprocessing system memory address), where the read input includes matchinput data (e.g., a cache tag) and a content-addressable memory elementselection index (e.g., a cache set index).

In the described method embodiment, match reference data correspondingto each of the emulated CAM elements is distributed among a number ofRAM elements. The match reference data is stored as portions of“one-hot” encoded match reference data within at least a first andsecond RAM element of the RAM elements used for CAM emulation. Recordswithin the first and second RAM elements are then identified using firstand second portions of the read input, respectively, along with the CAMelement selection index. The identified records are then used togenerate an emulated CAM read operation result (e.g., a match indicationsignal and/or match address).

FIG. 3 illustrates a RAM-based emulated CAM element according to anembodiment of the present invention. As distinguished from conventionalRAM-based CAM emulation systems, the “virtual” or emulated CAM element300 depicted in FIG. 3 may be used in place of a plurality oftraditional CAM elements rather than a single CAM element of a group.The functionality of emulated CAM element 300, as applied for performinga portion of a cache tag lookup operation, will now be described withrespect to data processing system processor cache 100 as illustrated in,and described with respect to, FIG. 1. Emulated CAM 300 of theillustrated embodiment includes RAM elements 302A-302F coupled withcombinatorial (e.g., AND gate 304 and OR gate 306) and encoding (e.g.,encoder 308) logic as shown.

Each RAM element 302 may be viewed as a 2-dimensional array of bitsincluding rows corresponding to each of the 64 ways of a cache memoryelement being accessed. Unlike a conventional RAM-based emulated CAMelement however, each RAM element row stores match reference data (e.g.,a “one-hot” encoded bit vector) for a portion of a cache tag associatedwith the row's associated way as well as for each CAM of the pluralityof CAMs being emulated. In other words, each row of RAM elements 302stores match reference data corresponding to a portion of a cache tagand to all “sets” of a set-associative cache upon which emulated CAMelement 300 is used to perform a cache tag lookup operation.

By exploiting the set associativity of a cache and storing matchreference data corresponding to each cache “set” within each RAM elementused, the size of each RAM element 302 is increased but the total numberof RAM elements 302 used is decreased as compared to conventionalmultiple-CAM element systems. Accordingly, a smaller number of bits oftotal storage capacity is required. In operation, emulated CAM 300 andassociated RAM elements 302 are utilized to perform a “split” lookupfunction in which separate portions (e.g., a 3-bit portion and 5 4-bitportions) of a cache tag along with a cache set index are used toaddress each of RAM elements 302. A match of a complete cache tag isindicated if each portion of the cache tag matches in the same way andset of the cache as determined using the match reference datadistributed among RAM elements 302.

For purposes of clarity, illustration of a write port has been omittedfrom emulated CAM element 300 of FIG. 3. In one embodiment of thepresent invention however, a separate RAM element is used to store priormatch reference data (e.g., in encoded form) which is used to identifyspecific bits to be cleared or “reset” prior to an update or writeoperation to the match reference data stored within RAM elements 302. Inemulated CAM element 300, each cache tag portion is used, along withassociated cache set index data, to identify or address a single bitposition. Each bit position may be viewed as a column within an accessedRAM element including a bit from each way of an associated cache. All 64bits of that bit position or column are then used to determine whetherthe provided or input partial cache tag value matched reference partialcache tag data within a specified set of a corresponding RAM element 302of emulated CAM 300 (indicated, for example, by a single bit having alogical “1” value).

The 64-bit outputs of each of RAM elements 302A-302F are then logicallycombined or “joined” via a bitwise AND operation using AND gate 304. Thecombined 64-bit output may then be used to generate a 6-bit matchaddress corresponding to a matching emulated CAM element record (e.g.,using encoder 308) and a match indication signal indicating whether ornot a matching record was identified (e.g., using OR gate 306). If noneof the bits of the bitwise-coalesced RAM element output is set to alogical “1” value, a determination may be made that the complete 23-bitinput cache tag failed to match an emulated CAM element entry for asingle way and set of an associated cache memory element.

According to one embodiment of the present invention, emulated CAMelement 300 may be implemented using conventional RAM elements coupledwith data processing system software or combinatorial logic. Suchcombinatorial logic may be implemented using discrete elements or aprogrammable logic device (PLD). In another embodiment, emulated CAMelement 300 may be implemented using a PLD. For example, emulated CAM300 may comprise one or more field programmable gate array (FPGA)elements such as a Virtex™-II FPGA device, provided by XilinxCorporation of San Jose, Calif.. Moreover, although individual RAMelements are depicted with respect to the described embodiments, asingle RAM element partitioned into multiple storage areas may besimilarly employed in alternative embodiments of the invention.

FIG. 4 illustrates a flow diagram of a process for emulating a readoperation on a plurality of content-addressable memory elementsaccording to an embodiment of the present invention. Although the flowdiagram depicted in FIG. 4 indicates a particular order of operation anda specific granularity of process operations, in alternative embodimentsthe illustrated order may be varied (e.g., process operations may beperformed in another order or performed substantially in parallel withone another) and one or more of the process operations may be coalescedor fragmented. Similarly, additional process operations may be added oreliminated where necessary in alternative embodiments of the presentinvention.

In the illustrated process embodiment, RAM elements used to emulate aplurality of CAM elements are first initialized with match referencedata (process block 402). Once initialization is complete, a read input(e.g., a data processing system memory address or portion thereof) isreceived (process block 404). According to alternative embodiments ofthe present invention, such input data may be provided to a cachecontroller element or directly applied to an input or read port of anemulated CAM element (e.g., emulated CAM 300 of FIG. 3). Thereafter, thereceived read input is parsed to identify match input data (e.g., cachetag) portions and a CAM element selection (e.g., cache set) index(process block 406).

Once the received read input has been parsed, each of a number ofassociated RAM elements is addressed using the CAM selection index alongwith a corresponding portion of the identified match input data (processblock 408). According to one embodiment, the described addressingoperation is performed by generating a RAM element address via aconcatenation of a cache set index with a predetermined number of cachetag bits and applying the generated RAM element address to an associatedRAM element read port. As each RAM element is addressed, a RAM elementrecord is identified containing match reference data for analysis todetermine whether an applied portion of match input data “matches”(i.e., is consistent with) match reference data within that RAM element.

According to one embodiment of the present invention, an identifiedrecord may be viewed as a column of bits within a 2-dimensional arrayincluding rows corresponding to each way of a set associative cache andcolumns corresponding to a combination of a cache set index and aportion of a cache tag. An identified record is then output by each ofthe described RAM elements. The RAM element outputs (e.g., “one-hot”encoded bit vectors) are next combined (process block 410) according tothe illustrated process embodiment of FIG. 4, for example, by performinga bit-wise logical AND operation.

Thereafter, the combined RAM element outputs are utilized to generate amatch indication signal and, if a match is determined to have occurredfor all portions of the received match input data, a match addressspecifying a location at which the matching data is stored within a CAMelement being emulated (process block 412). In one embodiment, a matchindication signal is generated by performing a logical addition or “OR”operation on the combined RAM element output. Similarly, in thedescribed embodiment, a match address is formed via encoding, forexample, by converting the previously “one-hot” encoded data to aconventional binary representation.

Once the match address and match indication signal have been generatedfor a received read input, match reference data within the RAM elementscomprising an associated emulated CAM may be updated (process block 414)if appropriate, before another read input is received for processing asshown. In one embodiment of the present invention, a match referencedata update is performed by first erasing or “clearing” an existing“one-hot” encoded bit (identifying the storage location of the databeing read) and subsequently writing or “setting” another bit within theRAM element as appropriate. In another embodiment, data identifyingpreviously-stored match reference data is stored within a separate RAMelement and used to identify which bit position is to be cleared at theoutset of a match reference data update operation.

While described primarily herein with respect to operation with a dataprocessing system processor cache (e.g., a cache tag lookup operation)embodiments of the present invention are applicable to a number of CAMelement-based search intensive functions. For example, embodiments ofthe present invention may be used in conjunction with CAM-based dataprocessing system processor translation lookaside buffers (TLBs), datacompression systems, database accelerators, neural networks, and/orcommunications network elements (e.g., to perform network/InternetProtocol (IP) address translation). Similarly, while fixed orpredetermined read input segments or portions have been illustrated anddescribed herein, such elements (e.g., match input data portions and/orCAM element selection indices) may be dynamically determined oridentified. For example, in one embodiment, a pool of available RAMelements may be selectively activated as needed to perform a particularCAM function with the sizes of the portions of match input data appliedto each RAM element being adjusted accordingly on a dynamic basis. Inanother exemplary embodiment, predetermined “header” data may be used todynamically specify the size and locations of a CAM selection indexand/or match input data.

While particular embodiments of the present invention have been shownand described, it will be obvious to those skilled in the art that,based upon the teachings herein, changes and modifications may be madewithout departing from this invention and its broader aspects and,therefore, the appended claims are to encompass within their scope allsuch changes and modifications as are within the true spirit and scopeof this invention.

Consequently, the invention is intended to be limited only by the scopeof the appended claims, giving full cognizance to equivalents in allrespects.

1. An apparatus for emulating a read operation on a plurality ofcontent-addressable memory elements utilizing a read input, wherein saidread input comprises match input data and a content-addressable memoryelement selection index, said apparatus comprising: means fordistributing match reference data among a plurality of random-accessmemory elements, wherein said means for distributing includes means forstoring match reference data corresponding to each of said plurality ofcontent-addressable memory elements within a first random-access memoryelement of said plurality of random-access memory elements; means foridentifying a first record within said first random-access memoryelement utilizing a first portion of said match input data and saidcontent addressable memory element selection index; and means forgenerating a read operation result utilizing said first record; wherein:said means for distributing further includes means for storing matchreference data corresponding to each of said plurality ofcontent-addressable memory elements within a second random-access memoryelement of said plurality of random-access memory elements, saidapparatus further comprises means for identifying a second record withinsaid second random-access memory element utilizing a second portion ofsaid match input data and said content addressable memory elementselection index, and said means for generating includes means forgenerating said read operation result utilizing said first record andsaid second record.
 2. The apparatus of claim 1, wherein said matchreference data comprises cache tag match reference data.
 3. Theapparatus of claim 2, wherein said read input data comprises a dataprocessing system memory address; said match input data comprises cachetag data of said data processing system memory address; and said contentaddressable memory element selection index comprises a cache set indexof said data processing system memory address.
 4. The apparatus of claim3, wherein said means for identifying said first record comprises meansfor identifying first cache tag match reference data of said cache tagmatch reference data within said first random-access memory element,said means for identifying said second record comprises means foridentifying second cache tag match reference data of said cache tagmatch reference data within said second random-access memory element,and said means for generating said read operation result utilizing saidfirst record and said second record comprises means for logicallycombining said first cache tag match reference data and said secondcache tag match reference data.
 5. The apparatus of claim 3, whereinsaid means for generating said read operation result comprises means forgenerating a cache tag lookup result and said apparatus furthercomprises means for accessing a cache memory element utilizing saidcache tag lookup result.
 6. An apparatus for emulating a read operationon a plurality of content-addressable memory elements utilizing a readinput, wherein said read input comprises match input data and acontent-addressable memory element selection index, said apparatuscomprising: a first random-access memory element to store a first matchreference data record, wherein said first random-access memory elementincludes: a read input port to receive a first portion of said matchinput data and said content-addressable memory element selection index;and a read output port to present said first match reference datarecord; a second random-access memory element to store a second matchreference data record, wherein said second random-access memory elementincludes: a read input port to receive a second portion of said matchinput data and said content-addressable memory element selection index;and a read output port to present said second match reference datarecord; and combinatorial logic, coupled to said first random-accessmemory element and said second random-access memory element, to generatea read operation result utilizing said first record and said secondrecord; wherein said read input data comprises a data processing systemmemory address; said match input data comprises cache tag data of saiddata processing system memory address; and said content addressablememory element selection index comprises a cache set index of said dataprocessing system memory address.
 7. The apparatus of claim 6, whereinsaid combinatorial logic comprises a logical AND gate element.